Field of the Invention
The present invention relates to methods and apparatus for determining edge placement error of a process in the manufacture of devices using lithographic techniques and to methods of manufacturing devices using lithographic techniques. Edge placement error may arise in any of the individual steps in a process for the manufacture of a device. For example, edge placement error can happen as a result of any step in the (dual) damascene process which includes several steps.
Background Art
A lithographic apparatus is a machine in a process for applying a desired pattern onto a substrate and/or in one or more layers on the substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., including part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In lithographic processes, it is desirable frequently to make measurements of the structures created, e.g., for process control and verification. Various tools for making such measurements are known, including scanning electron microscopes, which are often used to measure critical dimension (CD), and specialized tools to measure overlay (the accuracy of alignment of two or more layers in a device) and defocus of the lithographic apparatus. Recently, various forms of scatterometers have been developed including those for use in the lithographic field. These devices direct a beam of radiation onto a target and measure one or more properties of the scattered radiation—e.g., intensity at a single angle of reflection as a function of wavelength; intensity at one or more wavelengths as a function of reflected angle; or polarization as a function of reflected angle—to obtain a set of data from which a property of interest of the target can be determined. Determination of the property of interest may be performed by various techniques: e.g., reconstruction of the target structure by iterative approaches such as rigorous coupled wave analysis or finite element methods; library searches; and principal component analysis.
A useful parameter to measure is the so called edge placement error (EPE). This refers to the difference in the actual placement of an edge of a feature in a product structure compared to the desired placement. If edge placement error is not well controlled, contact between features in different layers is deleteriously affected. For example, it may be that features of different layers are no longer in contact when they are desired to be in contact in the finished product. For example, if the size of a feature is different to the desired size, that can mean that a feature in an adjacent layer is erroneously not in contact with it, even if the placement of the adjacent layer relative to the layer in which the feature is positioned is as desired. Conversely, even if a dimension of a feature is accurate, if the positioning of two adjacent layers is inaccurate, this again can mean that a contact which is desired to be there can be missing. So edge placement error is affected by the overlay error and the critical dimension.
Prior art direct measurement techniques for edge placement error are destructive techniques in which a cross section of a substrate is taken and the edge placement error measured using, for example, scanning electron microscopy. Edge placement error may be measured indirectly by measuring overlay and critical dimension. This technique relies on separate measurements of the contributors to the edge placement error. The overlay and critical dimensions are already measured separately using specific test patterns that can be measured without destroying the substrate. However, such specific test patterns often have a different dimension and pitch to the dimensions and pitch of the relevant features within the actual product. Both imaging as well as other processing effects have a contribution to overlay performance that depends on the dimension and pitch of features. Therefore, the difference in dimension and pitch between the specific test patterns for overlay and critical dimension measurement and those of the product limits any correlation between the measurement made on the specific test pattern and the actual overlay error within the product structure.
After a structure has been produced, it is possible to verify contact between features of a device or a test structure using contact probes to connect to the features and to get an analyzer to analyse the structure of the substrate. However, such a process is time consuming and so limits the ability to change the processing conditions of subsequent substrates to account for the measured edge placement error.
The targets used by conventional scatterometers are relatively large gratings, e.g., 40 μm by 40 μm, and the measurement beam generates a spot that is smaller than the grating (i.e., the grating is underfilled). This simplifies mathematical reconstruction of the target as it can be regarded as infinite. However, in order to reduce the size of the targets, e.g., to 10 μm by 10 μm or less, e.g., so they can be positioned in amongst product features, rather than in the scribe lane, metrology has been proposed in which the grating is made smaller than the measurement spot (i.e., the grating is overfilled). Typically such targets are measured using dark-field scatterometry in which the zeroth order of diffraction (corresponding to a specular reflection) is blocked, and only higher orders processed. Examples of dark-field metrology can be found in international patent applications WO 2009/078708 and WO 2009/106279 which documents are hereby incorporated by reference in their entirety. Further developments of the technique have been described in patent publications US20110027704A, US20110043791A and US20120123581A. The contents of all these applications are also incorporated herein by reference.
Diffraction-based overlay using dark-field detection of the diffraction orders enables overlay measurements on smaller targets. These targets can be smaller than the illumination spot and may be surrounded by product structures on a wafer. Multiple targets can be measured in one image.